This invention relates to segmentation of bitlines in integrated-circuit logic memory arrays.
The speed of access to information contained in non-volatile memory arrays is largely dependent on the capacitance of the bitlines and the wordlines. Those capacitances are a function of choices that include the lengths of the bitlines and wordlines, pitch, bar size and aspect ratio, and process parameters. In general, small capacitances are required for fast access time during operation of memory arrays. Conventional segmentation with separate driver circuitry for each segmented wordline and for each segmented bitline is generally impermissible because that method of reducing the access time delay requires an unacceptable increase in driver circuit area on integrated circuit chips.
Virtual-ground arrays, such as those of U.S. Pat. No. 4,281,397 issued July 28, 1981 and assigned to Texas Instruments Incorporated, permit a very efficient use of space for memory cells. As the size of each floating-gate memory cell decreases and as the number of memory elements in each row and each column increases, the lengths of the wordlines and bitlines generally remain the same. Therefore, the capacitance and the access time delay associated with those bitlines and wordlines also remain the approximately the same. However, as the number of cells increases, there is a need for a smaller access time delay in retrieving the increased amount of information contained in the dense memory arrays.
Accordingly, there is a need for a circuit arrangement that permits rapid access time during operation of virtual-ground memory circuit arrays while at the same time minimizing the increase in area required for driver circuitry on those arrays.